The present invention relates to an insulated-gate field effect transistor and a method of driving the same.
As one of methods for effectively accomplishing a low power consumption in an integrated circuit, there is a method of decreasing a power supply voltage. The gate threshold voltage V.sub.th in an MOS integrated circuit is generally 0.4 to 0.6 volt. When the method of decreasing a power supply voltage is applied to an MOS integrated circuit and the power supply voltage is equal to, or less than, 1 volt, therefore, there arises a problem that the operation speed of an MOS transistor element decreases. Further, when the gate threshold voltage V.sub.th is decreased (e.g., to about 0.2 volt) for decreasing a power supply voltage, leakage current caused by sub-threshold current flows even when the MOS transistor element is in an off-state, a stand-by current is no longer negligible, and there is caused a limit in decreasing power consumption. As a technology for preventing the flow of leakage current even when the MOS transistor element is in an off-state, the following technology is known.
That is, as a first prior art, as shown in FIG. 21, there is known a method in which an MOS transistor element TR.sub.1 having a low gate threshold voltage V.sub.th-L and an MOS transistor element TR.sub.2 having a high threshold voltage V.sub.th-H are combined, and when the MOS transistor element TR.sub.1 in a circuit block is not operated, the occurrence of leakage current in the MOS transistor element TR.sub.1 is inhibited by bringing the MOS transistor element TR.sub.2 into an off-state.
In a second prior art, as FIG. 22 shows an equivalent circuit and a schematic cross sectional view, a channel forming region is connected to a gate portion, and the gate threshold voltage V.sub.th of an MOS transistor element is set at a value close to conventional ones. And, the channel forming region is biased to a forward direction with a voltage of an input signal, whereby the gate threshold voltage V.sub.th is controlled so as to have a small value.
As a third prior art, as shown in FIG. 23, there is known a method in which a voltage of a channel forming region (well in FIG. 23) of an MOS transistor element or an MOS transistor element block is controlled, thereby to change the gate threshold voltage V.sub.th-ON when the transistor element is in an on-state and the gate threshold voltage V.sub.th-OFF when the transistor element is in an off-state. That is, there is used a phenomenon in which, for an n-channel transistor, when the voltage of the channel forming region (well) is decreased, the gate threshold voltage increases (that is, a high V.sub.th-OFF is obtained and the occurrence of leakage current is prevented) and when the voltage of the channel forming region (well) is increased, the gate threshold voltage decreases (that is, a low V.sub.th-ON is obtained and a decrease in a power supply voltage is accomplished).
The above first prior art or the above third prior art has the following problem. In addition to a conventional circuit for driving an MOS transistor element, it is required to provide a circuit for controlling the gate portion of the MOS transistor element TR.sub.2 having a high gate threshold voltage V.sub.th-H in the first prior art, or, it is required to design a circuit for controlling the voltage of the channel forming region (well) individually corresponding to a logic circuit in the third prior art, and procedure in designing of an integrated circuit system is complicated.
On the other hand, in the above second prior art, the channel forming region and the source portion in the MOS transistor element formed in a silicon semiconductor substrate are forward-biased, and therefore, when a voltage of an input signal exceeds the forward voltage in a junction portion between the channel forming region and the source portion, the voltage of the input signal is clamped. That is, the problem is that the voltage of the input signal is clamped around 0.6 volt at the highest even if it is high. In other word, the problem is that the amplitude of the input signal is limited. Further, the second prior art also involves a problem that when the power supply voltage is close to the gate threshold voltage V.sub.th, some MOS transistor elements may not operate due to temperature dependence on the gate threshold voltage V.sub.th, a variation among production lots and an in-plane variation on a wafer. That is because the channel forming region is connected to the gate portion so that, essentially, the gate threshold voltage V.sub.th when the voltage between the gate portion and the source portion is, e.g., 0 volt cannot be controlled so as to be a desired value after the MOS transistor element is produced.
Generally, the gate threshold voltage V.sub.th of an MOS transistor element is defined by controlling an impurity concentration in a channel forming region. In general, impurity is introduced into the channel forming region by ion implantation. With an increase in the integration degree of an integrated circuit, design rule of an integrated circuit is further and further is decreased, and the absolute amount of the impurity atoms ion-implanted into the channel forming region decreases. In the ion implantation, essentially, the amount of the impurity atoms in ion implantation has a fluctuation. Therefore, the degree of fluctuation from an average value of an impurity concentration increases, and as a result, the variation in the gate threshold voltage V.sub.th of an MOS transistor element, caused by the above fluctuation, increases. In an integrated circuit having 1000000 transistor elements having a gate length of 0.1 .mu.m, one simulation result shows that the variation in the gate threshold voltage V.sub.th is as large as 0.6 volt.